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Romain Danneau(Redirected from O.V. Lounasmaa Laboratory:VCSELs) » VCSELs

VCSELs

VCSEL's

1999 Four month project with the Centre d’Etude National des Télécommunications (CNET/FRANCE TELECOM, Bagneux Laboratory, Concepts and Devices for Photonics, now LPN in Marcoussis, France).

Supervisor: C. Mériadec and J.L. Oudar

Subject: Development of a Reactive Ion Etching (RIE) process on III-V semiconductor multi-layers and its application to the fabrication of vertical cavity devices (VCSEL's)

Part of my Master’s degree, I developped a new process for non-monolithic VCSEL's. This was my first steps in the clean room. This work was published three years later (see list of publications).

SEM and HRTEM micrographs of some Bragg mirrors

Scanning electron microscope micrograph of a 7.3 micron height mesa etched on a GaAs/AlxGa1-xAs Bragg mirror by SiCl4 RIE process. From H. Moussa et al., J. Vac. Sci. Technol. A 20(3), 748 (2002) [1].

This HRTEM photo shows the thin amorphous layer composed of native oxide formed after etching immediately when the sample takes contact with air. From H. Moussa et al., J. Vac. Sci. Technol. A 20(3), 748 (2002) [2].

Related publications:

• H. Moussa, R. Danneau, C. Mériadec, L. Manin, I. Sagnes and R. Raj

Deep in situ dry-etch monitoring of III-V multilayer structures using laser reflectometry and reflectivity modeling

J. Vac. Sci. Technol. A 20(3), 748 (2002) [3]