--- a/arch/mips/pci/pci-lantiq.c
+++ b/arch/mips/pci/pci-lantiq.c
@@ -153,7 +153,14 @@ static void ltq_pci_setup_gpio(struct de
 		}
 	}
 	ltq_gpio_request(dev, 21, 0, 1, "pci-reset");
-	ltq_pci_req_mask = (conf->gpio >> PCI_REQ_SHIFT) & PCI_REQ_MASK;
+
+	/* IMPORTANT! For Danube the bits actually correspond to PCI_REQ pin shared with EBU (?),
+	   PCI_REQ1, PCI_REQ2, and PCI_REQ3, from least to most significant bit. Current implementation
+	   has PCI_REQ1, PCI_REQ2, PCI_REQ3, and PCI_REQ4 (which does not exist on Danube).
+	   Maybe it's different on AR9/VR9? */
+
+	/* ltq_pci_req_mask = (conf->gpio >> PCI_REQ_SHIFT) & PCI_REQ_MASK; */
+	ltq_pci_req_mask = 0xf;
 }
 
 static int __devinit ltq_pci_startup(struct device *dev)